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| DR8051CPU High Performance 8-bit Microcontroller ver 3.10 OVERVIEW DR8051CPU is a high performance, area optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about low power consumption. Additionally an advanced power management unit makes DR8051CPU core perfect for portable equipment where low power consumption is mandatory. DR8051CPU soft core is 100% binarycompatible with the industry standard 8051 8bit microcontroller. There are two configurations of DR8051CPU: Harward where external data and program buses are separated, and von Neumann with common program and external data bus. DR8051CPU has RISC architecture 6.7 times faster compared to standard architecture and executes 65-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked up to seven times more slowly than the original implementation for no performance penalty. DR8051CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow. All trademarks mentioned in this document are trademarks of their respective owners. CPU FEATURES 100% software compatible with industry standard 8051 RISC architecture enables to execute instructions 6.7 times faster compared to standard 8051 12 times faster multiplication 9.6 times faster division Up to 256 bytes of internal (on-chip) Data Memory Up to 64K bytes of Program Memory Up to 16M bytes of external (off-chip) Data Memory User programmable Program Memory Wait States solution for wide range of memories speed User programmable External Data Memory Wait States solution for wide range of memories speed De-multiplexed Address/Data bus to allow easy connection to memory Interface for additional Special Function Registers Fully synthesizable, static synchronous design with positive edge clocking and no internal tri-states http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Scan test ready 1.3 GHz virtual clock frequency in a 0.35u technological process CONFIGURATION The following parameters of the DR8051CPU core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. * Memory style * Program Memory type * Program Memory waitstates - Harward - von Neumann - synchronous - asynchronous - used (0-7) - unused - used - unused - synchronous - asynchronous - used (0-7) - unused subroutines location PERIPHERALS DoCDTM debug unit Processor execution control Run Halt Step into instruction Skip instruction Read-write all processor contents Program Counter (PC) Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware execution breakpoints Program Memory Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory Hardware breakpoints activated at a certain Program address (PC) Address by any write into memory Address by any read from memory Address by write into memory a required data Address by read from memory a required data Three wire communication interface * Program Memory writes * Internal Data Memory type * External Data Memory wait-states * Interrupts * Power Management Mode * Stop mode * DoCD debug unit - used - unused - used - unused - used - unused DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance Power Management Unit Power management mode Switchback feature Stop mode Interrupt Controller 2 priority levels 2 external interrupt sources Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates http://www.DigitalCoreDesign.com http://www.dcd.pl All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Phone & email support SYMBOL clk reset ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr docddatao docdclk stop pmm LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Source Encrypted, or plain text EDIF called Netlist sfrdatai(7:0) prgdatai(7:0) xramdatai(7:0) int0 int1 docddatai One Year license for Encrypted Netlist only Unlimited Designs license for HDL Source Netlist BLOCK DIAGRAM clk reset prgdatai(7:0) prgdatao(7:0) prgdataz prgaddr(15:0) prgrd prgwr xramdatai(7:0) xramdatao(7:0) xramdataz xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramdatao(7:0) ramaddr(7:0) ramoe ramwe sfrdatai(7:0) sfrdatao(7:0) sfraddr(7:0) sfroe sfrwe Opcode Decoder ALU Upgrade from HDL Source to Netlist Single Design to Unlimited Designs Program Memory Interface Control Unit External Memory Interface Interrupt Controller int0 int1 Internal Data Memory Interface Power Management Unit stop pmm User SFR Interface DoCDTM Debug Unit docddatai docddatao docdclk All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. PINS DESCRIPTION PIN clk reset ramdatai[7:0] sfrdatai[7:0] prgdatai[7:0] xramdatai[7:0] int0 int1 docddatai ramdatao[7:0] ramaddr[7:0] ramoe ramwe sfrdatao[7:0] sfraddr[7:0] sfroe sfrwe prgaddr[15:0] prgdatao[7:0] prgdataz prgrd prgwr xramdatao[7:0] xramdataz xramaddr[23:0] xramrd xramwr docddatao docdclk pmm stop TYPE input input input input input input input input input output output output output output output output output output output output output output output output output output output output output output output DESCRIPTION Global clock Global synchronous reset Data bus from Internal Data Memory Data bus from user SFRs Input data bus from Program Memory Data bus from External Data Memory External interrupt 0 line External interrupt 1 line DoCDTM data input Data bus for Internal Data Memory Internal Data Memory address bus Internal Data Memory output enable Internal Data Memory write enable Data bus for user SFRs User SFRs address bus User SFRs output enable User SFRs write enable Program Memory address bus Output data bus for Program Memory PRGDATA tri-state buffers control line Program Memory read Program Memory write Data bus for External Data Memory XDATA tri-state buffers control line External Data Memory address bus External Data Memory read External Data Memory write DoCDTM data output DoCDTM clock line Power management mode indicator Stop mode indicator Program Memory Interface - Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new program into RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCDTM module. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. External Memory Interface - Contains memory access related registers such as Data Pointer High (DPH0), Data Pointer Low (DPL0), Data Page Pointer (DPP0), MOVX @Ri address register (MXAX) and STRETCH registers. It performs the memory addressing and data transfers. Allows applications software to access up to 16 MB of external data memory. The DPP0 register is used for segments swapping. STRETCH register allows flexible timing management while accessing different speed system devices by programming XRAMWR and XRAMRD pulse width between 1 - 8 clock periods. Internal Data Memory Interface - Internal Data Memory interface controls access into the internal 256 bytes memory. It contains 8-bit Stack Pointer (SP) register and related logic. User SFRs Interface - Special Function Registers interface controls access to the special registers. It contains standard and used defined registers and related logic. User defined external devices can be quickly accessed (read, written, modified) using all direct addressing mode instructions. Interrupt Controller - Interrupt control module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers. Power Management Unit - Block contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when http://www.DigitalCoreDesign.com http://www.dcd.pl UNITS SUMMARY ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic such as arithmetic unit, logic unit, multiplier and divider. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. Control Unit - Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks. All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. microcontroller is planned to use in portable and power critical applications. DoCDTM Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other onchip debuggers DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit addition (register addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 8-bit subtraction (register addressing) 8-bit multiplication 8-bit division 16-bit addition 16-bit subtraction 16-bit multiplication 32-bit addition 32-bit subtraction 32-bit multiplication Average speed improvement: Improvement 7,20 6,00 6,00 7,20 7,20 6,00 6,00 7,20 10,67 9,60 7,20 7,64 9,75 7,20 7,43 9,04 7,58 Dhrystone Benchmark Version 2.1 was used to measure Core performance. The following table gives a survey about the DR8051CPU performance in terms of Dhrystone/sec and VAX MIPS rating. Device 80C51 80C310 DR8051CPU Target 0.25u Clock Dhry/sec frequency (VAX MIPS) 12 MHz 268 (0.153) 33 MHz 1550 (0.882) 250 MHz 40325 (22.951) Core performance in terms of Dhrystones PERFORMANCE The following tables give a survey about the Core area and performance in ASICs Devices (all CPU features and peripherals have been included): Device 0.25u typical 0.25u typical Optimization area speed Fmax 100 MHz 250 MHz 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 80C51 (12MHz) DR8051CPU (250MHz) 40325 Core performance in ASIC devices 268 1550 For a user the most important is application speed improvement. The most commonly used arithmetic functions and their improvements are shown in table below. An improvement was computed as {80C51 clock periods} divided by {DR8051CPU clock periods} required to execute an identical function. More details are available in core documentation. 80C310 (33MHz) Area utilized by the each unit of DR8051CPU core in vendor specific technologies is summarized in table below. Component CPU* Interrupt Controller Power Management Unit Total area Area [Gates] [FFs] 4850 400 50 5300 220 40 5 265 *CPU - consisted of ALU, Opcode Decoder, Control Unit, Program & Internal & External Memory Interfaces, User SFRs Interface Core components area utilization All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. The main features of each DR8051 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Program Memory Wait States Architecture speed grade Compare/Capture Interrupt sources Stack space size Timer/Counters Interrupt levels Master I2C Bus Controller Slave I2C Bus Controller Design DR8051CPU DR8051 DR8051XP 6.7 64k 256 256 16M 6.7 64k 256 256 16M 6.7 64k 256 256 16M 2 5 15 2 2 2 1 1 2 2 3 1 2 4 4 - - - - - - DR8051 family of High Performance Microcontroller Cores The main features of each DR80390 family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Program Memory space Internal Data Memory space External Data Memory space External Data Memory Wait States Power Management Unit Interface for additional SFRs Program Memory Wait States Architecture speed grade Compare/Capture Interrupt sources Stack space size Timer/Counters Interrupt levels Master I C Bus Controller Slave I2C Bus Controller Design DR80390CPU 6.7 16M 256 256 16M DR80390 6.7 16M 256 256 16M DR80390XP 6.7 16M 256 256 16M 2 5 15 2 2 2 1 1 2 2 3 1 2 4 4 - - - - - - DR80390 family of High Performance Microcontroller Cores All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. Fixed Point Coprocessor Floating Point Coprocessor - Data Pointers Watchdog I\O Ports UART 2 SPI Fixed Point Coprocessor Floating Point Coprocessor - Data Pointers Watchdog I\O Ports UART SPI CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND e-mail: iinffo@dcd..pll n o@dc d p tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245, USA e-mail: iinffoUS@dcd..pll n oUS@dcd p tel. fax : +1 210 422 8268 : +1 210 679 7511 Distributors: Please check htttp::///www..dcd..pll//aparrttn..php h p www dcd p apa n php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. |
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